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Spring 2010 Seminars

February 9, 2010Dr. Ivan Lima, Electrical & Computer Engineering, NDSU

Advanced Monte Carlo Methods Applied to Optical Coherence Tomography

This presentation describes the biomedical imaging technique of optical coherence tomography (OCT) and shows some of the theoretical results of the application of importance sampling techniques applied to Monte Carlo simulations of light transport in multi-layered turbid media. The use of this method developed by the presenter allows a reduction of the computation time of the calculation of both the Class I diffusive reflectance, the OCT signal, and the Class II diffusive reflectance, the OCT noise, using Monte Carlo simulations by more than three orders of magnitude. This method has high potential to enable the development of signal processing techniques that can image organic tissues at significantly greater depths than are is possible using currently available OCT systems, which would extend the number of biomedical applications of this imaging technique.

February 23, 2010Michael Schmitz,
Graduate Student
Electrical and Computer Engineering, NDSU
An algorithm for optimizing the frequency distribution of an arbitrary multisine signal is presented to reduce the power consumption and computational complexity of a multisine receiver. By careful selection or adjustment of each frequency component in the applied multisine signal, undersampling and frequency aliasing in the receiver can be used to reduce the circuit power consumption contributed to operating frequency and also increase the bin utilization of the discrete Fourier transform (DFT) analysis frequencies. One example of an optimized 25-tone log-spaced multisine signal shows that the sampling frequency in the receiver can be reduced to only 4% of the Nyquist frequency. In addition, the computational complexity of calculating the DFT is reduced by a factor of 38.
March 4, 2010Professor Hamid R. Arabnia, Department of Computer Science, NDSU

Abstract: The two major issues in the formulation and design of parallel multiprocessor systems are algorithm design and architecture design. From an architectural point of view, the system should have low hardware complexity, be capable of being built of components that can be easily replicated, should exhibit desirable cost-performance characteristics, be cost effective and exhibit good scalability in terms of hardware complexity and cost with increasing problem size. In distributed memory multiprocessor systems, the processing elements can be considered to be nodes that are connected together via an interconnection network. In order to facilitate algorithm and architecture design, we require that the interconnection network have a low diameter, the system be symmetric and each node in the system have low degree of connectivity. Further, it is also desirable that the system configuration and behavior be amenable to a suitable and tractable mathematical description. The requirement of network symmetry ensures that each node in the network is identical to any other, thereby greatly reducing the architecture and algorithm design effort. For most symmetric network topologies, however, the requirements of low degree of connectivity for each node and low network diameter are often conflicting. Low network diameter often entails that each node in the network have a high degree of connectivity resulting in a drastic increase in the number of inter-processor connection links. A low degree of connectivity on the other hand, results in a high network diameter which in turn results in high inter-processor communication overhead and reduced efficiency of parallelism. Reconfigurable networks attempt to address this tradeoff. In a reconfigurable network each node has a fixed degree of active connectivity irrespective of the network size. The network diameter is restricted by allowing the network to reconfigure itself into different configurations. Broadly speaking, a reconfigurable system needs to satisfy the following criteria in order to be considered practically viable: (a) In each configuration the nodes in the network should have a fixed degree of active connectivity irrespective of network size, (b) The network diameter should be kept low via the reconfiguration mechanism and (c) The hardware for the reconfiguration mechanism (i.e. switch) should be of reasonable complexity. In this presentation, we discuss our design of a reconfigurable network topology that is targeted at problems in imaging science. We present some results and discuss the future roadmap of this project. We will also present our ongoing work which attempts to make the reconfiguration mechanism of the network seamless to the application programmer.

Biography: Hamid R. Arabnia is an author, editor of research books, educator, and researcher. He received a Ph.D. degree in Computer Science from the University of Kent (England) in 1987. Dr. Arabnia is a Full Professor of Computer Science at University of Georgia (Georgia, USA), where he has been since October 1987. His research interests include Parallel and distributed processing techniques and algorithms, interconnection networks, and applications. Dr. Arabnia is Editor-in-Chief of The Journal of Supercomputing (Springer) and is on the editorial and advisory boards of 25 other journals and magazines. He has published extensively in journals and refereed conference proceedings as well as edited numerous books. Dr. Arabnia has delivered many keynote lectures at international conferences; most recently at (since September 2008): The 14th IEEE International Conference on Parallel and Distributed Systems (ICPADS'08, Australia); International Conference on Future Generation Communication and Networking (FGCN 2008/IEEE CS, Sanya/China); and The 10th IEEE International Conference on High Performance Computing and Communications (HPCC-08, Dalian/China).

March 30, 2010Dr. Karen Pierce, Writing Specialist
Graduate School, NDSU

Graduate Writing Support Services and Disquisition Procedures

Abstract: Writing is an important part of graduate education, and almost all graduate students at NDSU complete a disquisition (Master's Paper, Master's Thesis, or Doctoral Dissertation) as part of their degree requirements. For some, writing is a daunting task, especially writing the disquisition. However, there are support services available at NDSU that can make writing more manageable, including writing and submitting the disquisition. This presentation will familiarize the audience with writing support services currently available to graduate students. The presentation will also review the Graduate School's Guidelines for Theses, Dissertations, and Papers and required submission dates and deadlines. The aim of this presentation is to disseminate information so that graduate students can feel confident about writing in general, as well as about writing and submitting the disquisition. Advisers can learn what services are available to students so that they might refer students to appropriate resources. A question and answer period will make up the conclusion of the presentation.

Biography: Karen P. Peirce is the Graduate Writing Coordinator at North Dakota State University, where she directs efforts to improve writing across the graduate curriculum. She got her start in the study of writing as an undergraduate consultant in the Writing Center at Rollins College, and she continued her focus on writing with an MA in Rhetoric from Carnegie Mellon University and a PhD in Rhetoric, Composition, and the Teaching of English from the University of Arizona. She has held faculty and administrative positions at the United States Military Academy and the University of Arizona, as well as at post-secondary and secondary educational institutions. She is Managing Editor of the journal FYHC: First Year Honors Composition, and her awards include a Fulbright English Teaching Assistantship to the Republic of Korea.

April 27, 2010Koushik Sarker,
Graduate Student
Electrical and Computer Engineering, NDSU

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