Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum Throughout the Nation

Overview


The development of synchronous circuits currently dominates the semiconductor design industry. However, there are major limiting factors to the synchronous, clocked approach, including the increasing difficulty of clock distribution, increasing clock rates, decreasing feature size, increasing power consumption, timing closure effort, and difficulty with design reuse. Asynchronous (clockless) circuits require less power, generate less noise, produce less electro-magnetic interference (EMI), and allow for easier reuse of components, compared to their synchronous counterparts, without compromising performance. As the demand continues for designs with higher performance, higher complexity, and decreased feature size, asynchronous paradigms will become more widely used in the industry, as evidenced by the International Technology Roadmap for Semiconductors’ (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues. The 2011 ITRS shows that asynchronous circuits accounted for 17% of chip area in 2010, compared to 11% in 2008, and estimates they will account for 23% of chip area by 2014, 35% by 2019, and 49% by 2024. Therefore, it is extremely important for Computer Engineering students to be introduced to asynchronous paradigms to make them more marketable and more prepared for the challenges faced by the digital design community for years to come.

Objectives

The goal of this project is to improve educational practices and student learning through development of materials that provide for easy integration of asynchronous concepts into existing course structures. No readily available educational materials currently exist for this topic. Following are the project's specific objectives:

  • Develop lecture notes, example problems, and group projects to introduce asynchronous paradigms,
  • Develop a VHDL library of fundamental asynchronous gates and components,
  • Develop static and semi-static transistor-level libraries of fundamental asynchronous gates,
  • Develop static and semi-static physical-level libraries of fundamental asynchronous gates,
  • Develop a Design-For-Test (DFT) library of fundamental asynchronous gates,
  • Develop NCL design and optimization CAD tools,
  • Develop an asynchronous FPGA
  • Integrate the developed materials into undergraduate-level courses at University of Arkansas, Missouri University of Science and Technology, and other institutions, and
  • Broadly disseminate the developed materials to faculty members at other institutions.
The developed materials will integrate cutting-edge technology into standard educational practices, to provide a low-cost, innovative addition to the Computer Engineering curriculum. The design modules focus on the delay-insensitive NULL Convention Logic (NCL) paradigm.

VHDL Library

VLSI Libraries

Mentor Graphics Libraries: 1.8V, 0.18um TSMC CMOS process

Cadence Libraries: 3.3V, 0.5um IBM 5AM BiCMOS process

Course Modules

  1. Intro to Asynchronous Logic:  Slides
  2. Intro to NCL:  Slides
  3. Transistor-Level NCL Gate Design:  Slides | Example Problems
  4. Input-Completeness and Observability:  Slides | Example Problems
  5. Dual-Rail NCL Design:  Slides | Example Problems
  6. Quad-Rail NCL Design:  Slides | Example Problems
  7. NCL Throughput Optimization:  Slides | Example Problems
  8. NCL Low Power Design:  Slides | Example Problems
  9. Group Projects
Professors: Please send us an email and we will gladly provide you with solutions to the example problems.

NCL Book

Scott C. Smith and Jia Di, Designing Asynchronous Circuits using NULL Convention Logic (NCL), Synthesis Lectures on Digital Circuits and Systems, Vol. 4/1, July 2009, Morgan & Claypool Publishers (doi: 10.2200/S00202ED1V01Y200907DCS023).

Asynchronous Publications

  1. V. Wijayasekara, A. Rollie, R. Hodges, S. Srinivasan, and S. C. Smith, "Abstraction Techniques to Improve Scalability of Equivalence Verification for NULL Convention Logic (NCL) Circuits," IET Electronics Letters, Vol. 52/19, pp. 1594-1596, September 2016.
  2. F. Parsan, S. C. Smith, and W. K. Al-Assadi, "Design for Testability of Sleep Convention Logic," IEEE Transactions on VLSI Systems, Vol. 24/2, pp. 743-753, February 2016.
  3. L. Zhou, S. C. Smith, and J. Di, "Radiation Hardened NULL Convention Logic Asynchronous Circuit Design," Journal of Low Power Electronics and Applications, Vol. 5/4, pp. 216-233, October 2015.
  4. R. S. P. Nair, S. C. Smith, and J. Di, "Delay Insensitive Ternary CMOS Logic for Secure Hardware," Journal of Low Power Electronics and Applications, Vol. 5/3, pp. 183-215, September 2015.
  5. L. Zhou, R. Parameswaran, F. Parsan, S. C. Smith, and J. Di, "Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology," Journal of Low Power Electronics and Applications, Vol. 5/2, pp. 81-100, May 2015.
  6. M. Linder, J. Di, and S. C. Smith, "Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L): A Low Overhead Secure IC Design Methodology," Journal of Low Power Electronics and Applications, Vol. 3/4, pp. 300-336, October 2013.
  7. M. Hinds, B. Sparkman, J. Di, and S. C. Smith, "An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency," Journal of Low Power Electronics, Vol. 9/2, pp. 175-188, August 2013.
  8. W. Cilio, J. Di, S. C. Smith, and D. R. Thompson, "Mitigating Power- and Timing-based Side-Channel Attacks Using Dual-Spacer Dual-Rail Delay-Insensitive Asynchronous Logic," Elsevier's Microelectronics Journal, Vol. 4/3, pp. 258-269, March 2013.
  9. F. Parsan, W. K. Al-Assadi, and S. C. Smith, "Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits," IEEE Transactions on VLSI, Vol. 22/1, pp. 99-112, December 2013.
  10. S. C. Smith, W. K. Al-Assadi, and J. Di, "Integrating Asynchronous Digital Design into the Computer Engineering Curriculum," IEEE Transactions on Education, Vol. 53/3, pp. 349-357, August 2010.
  11. A. Bailey, A. Al Zahrani, G. Fu, J. Di, and S. C. Smith, "Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power,” Journal of Low Power Electronics, Vol. 4/3, pp. 337-348, December 2008.
  12. V. Satagopan, B. Bhaskaran, A. Singh, and S. C. Smith, "Energy Calculation and Estimation for Delay-Insensitive Digital Circuits," Elsevier’s Microelectronics Journal, Vol. 38/10-11, pp. 1095-1107, October/November 2007.
  13. V. Satagopan, B. Bhaskaran, W. K. Al-Assadi, S. C. Smith, and S. Kakarla, "DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits," IEEE Transactions on VLSI Systems: Special Issue on System on Chip Integration, Vol. 15/10, pp. 1155-1159, October 2007.
  14. S. C. Smith, "Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits," IEEE Transactions on VLSI Systems, Vol. 15/6, June 2007.
  15. S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," Elsevier's Microelectronic Engineering Journal: Special Issue on VLSI Design and Test, Vol. 84/2, pp. 280-287, February 2007.
  16. S. C. Smith, "Speedup of NULL Convention Digital Circuits Using NULL Cycle Reduction," Elsevier's Journal of Systems Architecture, Vol. 52/7, pp. 411-422, July 2006.
  17. S. C. Smith, "Development of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit," Elsevier's Integration, The VLSI Journal, Vol. 39/1, pp. 12-28, September 2005.
  18. S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, "Optimization of NULL Convention Self-Timed Circuits," Elsevier's Integration, The VLSI Journal, Vol. 37/3, pp. 135-165, August 2004.
  19. S. K. Bandapati, S. C. Smith, and M. Choi, "Design and Characterization of NULL Convention Self-Timed Multipliers," IEEE Design and Test of Computers: Special Issue on Clockless VLSI Design, Vol. 30/6, pp. 26-36, November-December 2003. Figures
  20. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "NULL Convention Multiply and Accumulate Unit with Conditional Rounding, Scaling, and Saturation," Elsevier's Journal of Systems Architecture, Vol. 47/12, pp. 977-998, June 2002.
  21. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "Delay-Insensitive Gate-Level Pipelining," Elsevier's Integration, the VLSI Journal, Vol. 30/2, pp. 103-131, October 2001.
  22. A. A. Sakib, S. C. Smith, and S. K. Srinivasan, "Formal Modeling and Verification for Pre-Charge Half Buffer Gates and Circuits," IEEE International Midwest Symposium on Circuits and Systems, pp. 519-522, August 2017.
  23. N. S. Balaneji and S. C. Smith, "Analysis and Design of CMOS Resettable C-Elements," IEEE International Midwest Symposium on Circuits and Systems, pp. 104-107, August 2017.
  24. V. Wijayasekara, S. K. Srinivasan, and S. C. Smith, "Equivalence Verification for NULL Convention Logic (NCL) Circuits," 32nd IEEE International Conference on Computer Design (ICCD), pp. 195-201, October 2014.
  25. F. Parsan, J. Zhao, and S. C. Smith, "SCL Design of a Pipelined 8051 ALU," IEEE International Midwest Symposium on Circuits and Systems, pp. 885-888, August 2014.
  26. B. Sparkman, M. Hinds, J. Di, and S. C. Smith, "An Asynchronous AES Core Design for Energy Efficiency," SRC TECHCON, accepted for publication April 2013.
  27. P. Palangpour and S. C. Smith, "Sleep Convention Logic Using Partially Slept Function Blocks," IEEE International Midwest Symposium on Circuits and Systems, pp. 17-20, August 2013.
  28. P. Varadharajan, W. K. Al-Assadi, S. F. Alam, and S. C. Smith, "Quantum-dot Cellular Automaton of Asynchronous Null Convention Logic Multiplier Design," IEEE International Midwest Symposium on Circuits and Systems, pp. 813-816, August 2013.
  29. Z. Song and S. C. Smith, "Implementation of a Fast Fourier Transform Processor in NULL Convention Logic," International Conference on Computer Design, pp. 10-16, July 2013.
  30. P. Shepherd, S. C. Smith, J. Holmes, A. M. Francis, N. Chiolino, and H. A. Mantooth, "Robust, Wide-Temperature Data Transmission System for Space Environments," IEEE Aerospace Conference, pp. 1-13, March 2013.
  31. F. Parsan and S. C. Smith, "CMOS Implementation of Static Threshold Gates with Hysteresis: A New Approach," IFIP/IEEE International Conference on VLSI-SoC, pp. 41-45, October 2012.
  32. J. T. Roark and S. C. Smith, "Demonstration of the Benefit of Asynchronous vs. Synchronous Circuits," ASEE Midwest Section Conference, September 2012.
  33. F. Parsan and S. C. Smith, "CMOS Implementation Comparison of NCL Gates," IEEE International Midwest Symposium on Circuits and Systems, pp. 394-397, August 2012.
  34. L. Zhou and S. C. Smith, "Accurate Throughput Derivation of Pipelined NULL Convention Logic Asynchronous Circuits," International Conference on Computer Design, pp. 51-54, July 2012.
  35. B. Sparkman and S. C. Smith, "Reducing Energy Usage of NULL Convention Logic Circuits using NULL Cycle Reduction Combined with Supply Voltage Scaling," International Conference on Computer Design, pp. 3-8, July 2012.
  36. R. B. Reese, S. C. Smith, and M. A. Thornton, "Uncle - An RTL Approach to Asynchronous Design," IEEE International Symposium on Asynchronous Circuits and Systems, pp. 65-72, May 2012.
  37. M. Linder, J. Di, and S. C. Smith "MTD3L - A Secure IC Design Methodology with Reduced Overhead," International Conference on Microelectronics, Nanoelectronics, Optoelectronics, April 2012.
  38. L. Zhou and S. C. Smith, "Standby Power Reduction Techniques for Asynchronous Circuits with Indeterminate Standby States," International Conference on Computer Design, pp. 10-16, July 2011.
  39. B. Hollosi, J. Di, S. C. Smith, and H. A. Mantooth, "Delay-Insensitive Asynchronous Circuits for Operating under Extreme Temperatures," Government Microcircuit Applications & Critical Technology Conference, March 2011.
  40. S. C. Smith and J. Di, "Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum Throughout the Nation," NSF CCLI/ TUES PI Conference, January 2011.
  41. L. Zhou and S. C. Smith, "Static Implementation of Quasi-Delay-Insensitive Pre-Charge Half-Buffers," IEEE Midwest Symposium on Circuits and Systems, pp. 636-639, August 2010. (nominated for best student paper)
  42. L. Zhou, S. C. Smith, and J. Di, "Bit-Wise MTNCL: An Ultra-Low Power Bit-Wise Pipelined Asynchronous Circuit Design Methodology," IEEE Midwest Symposium on Circuits and Systems, pp. 217-220, August 2010.
  43. S. Yancey and S. C. Smith, "A Differential Design for C-Elements and NCL Gates," IEEE Midwest Symposium on Circuits and Systems, pp. 632-635, August 2010. (nominated for best student paper)
  44. S. C. Smith, D. Roclin, and J. Di, "Delay-Insensitive Cell Matrix," International Conference on Computer Design, pp. 67-73, July 2010.
  45. C. M. Smith and S. C. Smith, "Comparison of NULL Convention Booth2 Multipliers," International Conference on Computer Design, pp. 3-9, July 2010.
  46. W. A. Cilio, M. J. Linder, C. Porter, J. Di, and S. C. Smith, "Side-Channel Attack Mitigation Using Dual-Spacer Dual-Rail Delay-Insensitive Logic (D3L),” IEEE SoutheastCon, March 2010.
  47. B. Hollosi, T. Zhang, R. S. P. Nair, Y. Xie, J. Di, and S. C. Smith, "Investigation and Comparison of Thermal Distribution in Synchronous and Asynchronous 3D ICs," IEEE International Conference on 3D System Integration, September 2009.
  48. L. Zhou and S. C. Smith, “Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit,” IEEE Midwest Symposium on Circuits and Systems, pp. 499-502, August 2009.
  49. R. S. P. Nair, S. C. Smith, and J. Di, “Delay-Insensitive Ternary Logic," International Conference on Computer Design, pp. 3-9, July 2009.
  50. A. Bailey, J. Di, S. C. Smith, and H. A. Mantooth, "Ultra-Low Power Delay-Insensitive Circuit Design,” IEEE Midwest Symposium on Circuits and Systems, August 2008.
  51. B. Hollosi, M. Barlow, G. Fu, C. Lee, J. Di, S. C. Smith, H. A. Mantooth, and M. Schupbach, "Delay-Insensitive Asynchronous ALU for Cryogenic Temperature Environments,” IEEE Midwest Symposium on Circuits and Systems, August 2008.
  52. S. C. Smith, W. K. Al-Assadi, and J. Di, “Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum Throughout the Nation,” NSF CCLI PI Conference, August 2008.
  53. S. C. Smith and W. K. Al-Assadi, "Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum," 6th ASEE Global Colloquium on Engineering Education, October 2007.
  54. S. C. Smith and W. K. Al-Assadi, "Integrating Asynchronous Digital Design and Testing into the Undergraduate Computer Engineering Curriculum," The 2007 ASEE Annual Conference & Exposition, June 2007.
  55. S. C. Smith, "Design of a Logic Element for Implementing an Asynchronous FPGA," 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 13-22, February 2007.
  56. S. C. Smith and W. K. Al-Assadi, "Teaching Asynchronous Digital Design in the Undergraduate Computer Engineering Curriculum," IEEE Region 5 Technical Conference, April 2007.
  57. M. V. Joshi, S. Gosavi, V. Jagadeesan, A. Basu, S. Jaiswal, W. K. Al-Assadi, and S. C. Smith, "NCL Implementation of Dual-Rail 2s Complement 8×8 Booth2 Multiplier using Static and Semi-Static Primitives," IEEE Region 5 Technical Conference, April 2007.
  58. S. R. Mallepalli, S. Kakarla, S. Burugapalli, S. Beerla, S. Kotla, P. K. Sunkara, W. K. Al-Assadi, and S. C Smith, "Implementation of Static and Semi-Static Versions of a Quad-Rail NCL 24+8x8 Multiply and Accumulate Unit," IEEE Region 5 Technical Conference, April 2007.
  59. R. S. P. Nair, F. Kacani, R. Bonam, S. M. Gandla, S. K. Chitneni, V. Kadiyala, W. K. Al-Assadi, and S. C. Smith, "Implementation of Static and Semi-Static Versions of a Bit-Wise Pipelined Dual-Rail NCL 2s Complement Multiplier," IEEE Region 5 Technical Conference, April 2007.
  60. S. C. Smith, "Integrating Asynchronous Digital Design into the Undergraduate Computer Engineering Curriculum," The 2006 ASEE Midwest Section Annual Conference, September 2006.
  61. V. Satagopan, B. Bhaskaran, W. Al-Assadi, and S. C. Smith, "Automation in Design for Test for Asynchronous Null Conventional Logic (NCL) Circuits," 12th NASA Symposium on VLSI Design, October, 2005.
  62. B. Bhaskaran, V. Satagopan, and S. C. Smith, "High-Speed Energy Estimation for Delay-Insensitive Circuits," The 2005 International Conference on Computer Design, pp. 35-41, June 2005.
  63. A. Singh and S. C. Smith, "Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation," The 2005 International Conference on Computer Design, pp. 115-121, June 2005.
  64. B. Bhaskaran, V. Satagopan, W. Al-Assadi, and S. C. Smith, "Implementation of Design For Test for Asynchronous NCL Designs," The 2005 International Conference on Computer Design, pp. 78-84, June 2005.
  65. S. C. Smith, "Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput," The 2004 International Conference on VLSI, pp. 407-412, June 2004.
  66. S. C. Smith, "Design of a NULL Convention Self-Timed Divider," The 2004 International Conference on VLSI, pp. 447-453, June 2004.
  67. S. C. Smith, "Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-wise Completion Strategy," The 2003 International Conference on VLSI, pp. 143-149, June 2003.
  68. S. K. Bandapati and S. C. Smith, "Design and Characterization of NULL Convention Arithmetic Logic Units," The 2003 International Conference on VLSI, pp. 178-184, June 2003.
  69. S. C. Smith, "Speedup of Self-Timed Digital Systems Using Early Completion," The IEEE Computer Society Annual Symposium on VLSI, pp. 107-113, April 2002.
  70. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, "Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction," The 10th International Workshop on Logic and Synthesis, pp. 185-189, June 2001.

People

Principle Investigator: Scott C. Smith

Co-Principle Investigators: Jia Di and Waleed K. Al-Assadi

Graduate Assistants:

  • Bonita Bhaskaran, PhD
  • Mandar Joshi, MS
  • Sindhu Kakarla, MS
  • Samarsen Mallepalli, MS
  • Ravi Parameswaran, PhD/MS
  • Vijay Pillai, MS
  • Venkat Satagopan, PhD
  • Vipin Sharma, MS
  • Steven Yancey, PhD

Sponsor: National Science Foundation



The PIs gratefully acknowledge the support from the National Science Foundation under CCLI grants DUE-0536343, DUE-0717572, and DUE-0717767.

Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.

Contact Us

Electrical and Computer Engineering room 101B
PO Box 6050
Fargo, ND 58108-6050
Phone: (701) 231-7394
Fax: (701) 231-8677
E-Mail: scott.smith.1@ndsu.edu